TSMC puts 65-nm process into volume production

This article was published by the Taiwan Headlines on May 19, 2006. According to this article, Taiwan Semiconductor Manufacturing Co. (TSMC) recently announced that it had fully qualified its 65-nanometer low-power process technology for volume production. Indeed, TSMC was the first supplier in the international silicon-foundry industry to ready the 65-nm process for mass production.

According to TSMC, the company's 65-nm NexsysSM technology is a third-generation semiconductor process that employs both copper interconnects and low-k dielectrics. It is a nine-layer metal process with core voltages of 1.0 or 1.2 volts, and I/O voltages of 1.8, 2.5 or 3.3 volts. The new technology supports a standard cell gate density that is twice the number of TSMC's 90-nm NexsysSM process. Meanwhile, the 65-nm process technology also features very competitive 6T static random access memory (SRAM0 and 1T-embedded dynamic random access memory (DRAM) cell sizes.

With the 65-nm process, TSMC is able to produce highly integrated, small and lower-power devices for every conceivable market. The company's 65-nm process production can take off quickly because such production can be conducted at existing 300-mm wafer fabs. More significantly, production can be further boosted by the company's 65-nm design for manufacturing (DFM) service.

According to industry analysts, TSMC's introduction of the production-ready 65-nm process is expected to intensify competition in the advanced-process technology area. Indeed, TSMC's major rival, United Microelectronics Corp. (UMC), recently announced that it would sign up at least eight customers for its 65-nm process service and 11 tape-out products by the end of summer 2006.